CODE:

--------------------------------------------------
-----Library
--------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

--------------------------------------------------
-----Entity
--------------------------------------------------
entity ADCtrl is
	generic(	ADCBIT : integer := 11;
		ROMBIT : integer := 20;
		ADRSBIT : integer := 10;
		DATABIT : integer := 16);
	port(	CLK,RST : in std_logic;
		ADC_START : in std_logic;
		ADC_SEL : out std_logic;
		SAMPLING : in std_logic_vector(ADCBIT-1 downto 0);
		ADC_ADRS : out std_logic_vector(ADRSBIT-1 downto 0);
		ADC_DATA : out std_logic_vector(DATABIT-1 downto 0));
end entity;

--------------------------------------------------
-----Architecture
--------------------------------------------------
architecture RTL of ADCtrl is

	--------------------------------------------------
	-----Signal
	--------------------------------------------------
	signal count_half : unsigned(ADRSBIT-2 downto 0);
	signal count_fs : unsigned(ADRSBIT-1 downto 0);
	signal trig_delay1 : std_logic;
	signal trig_delay2 : std_logic;
	signal trig_delay3 : std_logic;
	signal trig_edge : std_logic;

begin

	Trig_Delay : process(CLK,RST)
	begin
		if(RST = '0')then
			trig_delay1  '0');
		elsif(CLK'event and CLK = '1')then
			count_half  '0');
		elsif(CLK'event and CLK = '1')then
			if(trig_edge = '1')then
				count_fs  '0');
			elsif(count_fs /= 1023 and count_half = 511)then
				count_fs <= count_fs + 1;
			end if;
		end if;
	end process;
	
	process(count_fs)
	begin
		for i in ADRSBIT-1 downto 0 loop
			ADC_ADRS(ADRSBIT-1-i) <= count_fs(i);
		end loop;
	end process;
	
	Cap_Sel_Gen : process(CLK,RST)
	begin
		if(RST = '0')then
			ADC_SEL <= '0';
		elsif(CLK'event and CLK = '1')then
			if(trig_edge = '1')then
				ADC_SEL <= '1';
			elsif(count_fs = 1023 and count_half = 511)then
				ADC_SEL <= '0';
			end if;
		end if;
	end process;
			
	--------------------------------------------------
	-----Data to Ram Controller
	--------------------------------------------------
	ADC_DATA <= "00000" & SAMPLING;

end RTL;